2.0) Technical Information:

2.1 - General Hardware Specs

Intellivision Master Component (these apply to the clones as well)

2.2 - Processor Specs

(Author's note: Most of this information was captured off the net two years ago, would the original author please speak up and maybe help me clean up this info?? =) )

GI 1600, running at something like 500KHz. Processor has 16 bit registers, uses 16 bit RAM, and has 10 (yes, 10) bit instructions. Intellivision cartridges contain ROMs that are 10 bits wide. Ten bits are called a decle, and half that is a nickle. There were 160 bytes of RAM, I think (general purpose RAM -- there is also RAM used by the graphics chip for character bitmaps and to tell what is where on the screen).

The CPU was strange. For example, if you did two ROTATE LEFT instructions, followed by a ROTATE RIGHT BY 2 (rotates could be by one or two), you did NOT end up with the original word. The top two bits were swapped!

Ken Kirkby also has this to add:

"The GI CP1600 was developed as a joint venture in the early seventies between GI and Honeywell. One of the first commercial uses of the CP1600 was its incorporation into Honeywell's TDC2000, the first distributed control system, prototypes existed in late '74 I think. Honeywell's then Test Instrument Division also incorporated into a Cardiac Catheterisation system called MEDDARS which was released for sale about 1979. The CP1600 was definitely a 16 bit chip."

John Dullea dug this information up during a stroll at his local library:

In the Penn State Library I found a book called "An Introduction to Microcomputers, Vol. 2: Some Real MicroProcessors", By Adam Osborne, Osborne & Associates, Inc., 1978. ISBN: 0-931998-15-2. Library of Congress catalogue card #: 76-374891. It has lots of info on the CP1600/1610 CPU in the Intellivision in chapter 16 (If you want a photocopy of the chapter, e-mail me). Here are the pinouts of the CPU:

                 +------------------+    ____ 
         EBCI ---+ 1             40 +--- PCIT 
        _____    |                  | 
        MSYNC ---+ 2             39 +--- GND 
                 |                  | 
          BC1 ---+ 3             38 +--- (PHI)1 
                 |                  | 
          BC2 ---+ 4             37 +--- (PHI)2 
                 |                  | 
         BDIR ---+ 5             36 +--- VDD 
                 |                  | 
          D15 ---+ 6             35 +--- VBB 
                 |                  | 
          D14 ---+ 7             34 +--- VCC 
                 |                  | 
          D13 ---+ 8             33 +--- BDRDY 
                 |                  |    _____ 
          D12 ---+ 9             32 +--- STPST 
                 |                  |    _____ 
          D11 ---+ 10            31 +--- BUSRQ 
                 |                  | 
          D10 ---+ 11            30 +--- HALT 
                 |                  |    _____ 
           D9 ---+ 12   CP1600   29 +--- BUSAK 
                 |       CPU        |    ____ 
           D8 ---+ 13            28 +--- INTR 
                 |                  |    _____ 
           D0 ---+ 14            27 +--- INTRM 
                 |                  | 
           D1 ---+ 15            26 +--- TCI 
                 |                  | 
           D7 ---+ 16            25 +--- EBCA0 
                 |                  | 
           D6 ---+ 17            24 +--- EBCA1 
                 |                  | 
           D5 ---+ 18            23 +--- EBCA2 
                 |                  | 
           D4 ---+ 19            22 +--- EBCA3 
                 |                  | 
           D3 ---+ 20            21 +--- D2 
                 +------------------+ 

D0-D15 ............... Data and address bus ................ Tristate, 
                                                             bidirectional 
BDIR, BC1, BC2 ....... Bus control signals ................. Output 
(PHI)1,(PHI)2 ........ Clock signals ....................... Input 
_____ 
MSYNC ................ Master synchronization .............. Input 
EBCA0-EBCA3 .......... External branch condition addr lines  Output 
EBCI ................. External branch condition input ..... Input 
____ 
PCIT ................. Program Counter inhibit/software .... Input 
                       interrupt signal 
                       ____ 
BDRDY ................ WAIT ................................ Input 
_____ 
STPST ................ CPU stop or start on high-to-low .... Input 
                       transition 
HALT ................. Halt state signal ................... Output 
____  _____ 
INTR, INTRM .......... Interrupt request lines ............. Input 
TCI .................. Terminate current interrupt ......... Output 
_____ 
BUSRQ ................ Bus request ......................... Input 
_____ 
BUSAK ................ External bus control acknowledge .... Output 
VBB, VCC, VDD, GND ... Power and ground

Whew!!!

Now...Looking at the logic board in the Intellivision unit (original model 2609) reveals a number of (important) chips:

Sound ............. AY-3-8914 ................ 40-pin 
ROM ............... RO-3-9503-003 ............ 40-pin 
ROM ............... RO-3-9502-011 ............ 40-pin 
Color ............. AY-3-8915 ................ 18-pin

And, of course, there is the cartridge ROM:

ROM ............... AY-3-9504-021 ............ 28-pin

In addition, there are three 40-pin chips that have heat sinks epoxied on top. Now, you may try this, but be EXTREMELY careful (or just listen to what I found): I carefully removed the three heat-sunk chips and looked at them; they have designations on the bottom!

STIC .............. AY-3-8900-1 .............. 40-pin 
RAM ............... RA-3-9600 ................ 40-pin 
CPU ............... CP-1610 .................. 40-pin  +----- hello!

Having the CPU location and pinouts, one can use an ohmmeter to map the pins to the cartridge pins:

(looking AT the cartridge, not the Intellivision unit)

You probably should double-check this, but I obviously can't accept any responsibility for any damage to your Master Component. (I'm not 100% sure about the assignments for VCC and GND.)

TOP                      BOTTOM 

         NC       GND 
                  _____ 
         NC       MSYNC 
         NC       D7 
        GND       D8 
        GND       D6 
        GND       D9 
         NC       D5 
        GND       D10 
        GND       D4 
        GND       D11 
        GND       D3 
        GND       D12 
        GND       D13 
        GND       D2 
         NC       D14 
         *1       D1 
         *2       D0 
         *3       D15 
         *3       *3 
         *2       *2 
         *1       *1 
        GND       VCC 

All *x pins are connected; cartridges have a loop on the top row connecting them, and the connector in the Intellivision unit connects the top row *x pins to those on the bottom row. Internally, *x pins are connected as follows:

*1 ............ STIC pin 7 
*2 ............ STIC pin 6 
*3 ............ STIC pin 8

There may be other connections to them as well; I don't know why they connect to the ROM pins. However, considering the system changer's ability to route in external video, having pins going to the STIC seems to make some sense. I suspect that they may switch the ROM from address write mode to data read mode (like the three bus control lines on the CPU, maybe).

Mapping this to the ROM pinouts, you get:

             +-------------------+ 
      VCC ---+ 1              28 +--- STIC pin 7 
             |                   | 
       NC ---+ 2              27 +--- STIC pin 6 
             |                   | 
       NC ---+ 3              26 +--- STIC pin 8 
             |                   | 
      D15 ---+ 4              25 +--- D0 
             |                   | 
       NC ---+ 5              24 +--- D1 
             |                   | 
      D14 ---+ 6              23 +--- D2 
             |                   | 
      D13 ---+ 7              22 +--- NC 
             |                   | 
      D12 ---+ 8              21 +--- D3 
             |                   | 
      D11 ---+ 9              20 +--- D4 
             |                   | 
      D10 ---+ 10             19 +--- D5 
             |                   | 
       NC ---+ 11             18 +--- NC 
             |                   | 
       D9 ---+ 12             17 +--- D6 
             |                   | 
       D8 ---+ 13             16 +--- D7 
    _____    |                   | 
    MSYNC ---+ 14             15 +--- GND 
             +-------------------+

Please note that the chapter mentioned above has all opcode and register info, as well as timing information for the CP1600/1600A/1610 CPUs.

2.3 - Graphics Specs

160x92 pixels, 16 colors, 8 sprites (they were called "moving objects" rather than sprites). I don't recall the sprite size -- I think it was 16x16. Sprites could be drawn with oversize pixels (I think they could be linearly doubled or quadrupled, but again, memory is hazy).

Graphics is character based. The screen is twelve rows of twenty characters. Characters either come from Graphics ROM (GROM), which contains the usual alphanumeric symbols and a bunch of other things meant to be useful in drawing backgrounds (256 characters in all), or Graphics RAM (GRAM), which the program can use to build pictures needed that aren't in GROM (like sprite images). GRAM can hold 64. The predesigned sprites located in ROM were a big help in speeding up gameplay. (Now that I think about it, maybe sprites were 8x16 -- I don't recall them taking up 4 pictures in GRAM -- but two seems reasonable.)

Eight of the colors are designated as the primary colors. The other eight are called the pastel colors.

There were two graphics modes: Foreground/Background, and Color Stack. In F/B mode, you specify the colors for both the on and off pixels of each card ("card" is the term for a character on the screen). One of these (the on pixels, I think) could use any color, but the other could only use the primary colors.

In CS mode, you can give the chip a circular list of four colors (pastels and primaries are both allowed). For each card, you specify the ON bits color from any of the 16 colors, and the OFF bits color comes from the next color on the circular list. You can also tell if the list is to advance or not. Thus, in CS mode, you only get four colors for the OFF bits, and they have to be used in a predetermined order, but you get to use the pastels. Most games used CS mode.

I seem to recall that a sprite could be designated as either being in front of or behind the background, which determined priority when it overlapped the ON pixels of a background image.

You could tell the graphics chip to black out the top row or the first column (or both) of cards. You could also tell it to delay the display by up to the time of seven scan lines, or to delay the pixels on each scan line by up to seven pixel times. Using these two features together allows for smooth scrolling.

For example, a game that is going to scroll a lot sideways could black out the first row. Now, to scroll the background to the right by one pixel, you just have to delay by one pixel time. This moves everything over. The black part is NOT delayed -- that is always displayed in the first 8 screen pixel locations. The net result is that you now see one pixel that was previously hidden under the black strip, and one pixel on the other side has fallen of the edge, and everything appears to have moved over. Thus, to scroll, you only have to move the screen memory every eighth time, when things need to be shifted a full card. There is no need for a bitblt-type operation.

The hardware detected collisions between sprites and other sprites or the background.

GRAM and (I think) screen memory could only be manipulated during vertical retrace. At the end of vertical retrace, you had to tell the chip if it should display or not. If you weren't done, you could keep manipulating by not telling it to display, but then you end up with a flicker. Unacceptable.

2.4 - Operating System Specs

The operating system did several things:

• It allowed the program to specify a velocity for each sprite. The OS would deal with adjusting the sprite position registers for you and cycling through your animation sequence.
  
• For each pair of sprites you could specify a routine to be called when that pair of sprites collided. For each sprite, you could specify a routine to be called when that sprite hit the background or the edge of the screen.
  
• It maintained timers, and allowed you to specify routines to be called periodically.
  
• It dealt with the controls. You could specify routines to be called when the control disc was pressed or released, or when buttons were pressed or released. It provided functions to read numbers from the keypad. The calling sequence for these were a bit strange. When you called these, they saved the return address, then did a return. You had to call them with nothing after your return address on the stack, and they return to your caller. When the number is ready, they return to after where you called them, but as an interrupt. In generic assembly, it would be like this (I've long since forgotten 1600!):

        jsr     foo 
        bar:
                ... 
                ... 
        foo:    ;do some setup or whatever 
        jsr     GetNumberFromKeypad 
        spam:   ...

GetNumberFromKeypad returns to bar immediately. When the number is read, spam will be called from an interrupt handler. If you didn't know that a routine did this, reading code could get rather confusing!

-------------------------------------------------------------------------- 
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| Larry Anderson - insane@shellx.best.com               | 
| Classic Games Collector with a bug for information =) | 
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